Central Processor Unit (CPU)
4.7 Instruction Set Summary
provides a summary of the M68HC08 instruction set.
Table 4-1. Instruction Set Summary (Sheet 1 of 6)
Address
Mode
Opcode
Source
Form
ADC #opr
ADC
opr
ADC
opr
ADC
opr,X
ADC
opr,X
ADC ,X
ADC
opr,SP
ADC
opr,SP
ADD #opr
ADD
opr
ADD
opr
ADD
opr,X
ADD
opr,X
ADD ,X
ADD
opr,SP
ADD
opr,SP
AIS #opr
AIX #opr
AND #opr
AND
opr
AND
opr
AND
opr,X
AND
opr,X
AND ,X
AND
opr,SP
AND
opr,SP
ASL
opr
ASLA
ASLX
ASL
opr,X
ASL ,X
ASL
opr,SP
ASR
opr
ASRA
ASRX
ASR
opr,X
ASR
opr,X
ASR
opr,SP
BCC
rel
Operation
Description
V H I N Z C
Add with Carry
A
←
(A) + (M) + (C)
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
AB
BB
CB
DB
EB
FB
9EEB
9EDB
A7
AF
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
ii
ii
ii
dd
hh ll
ee ff
ff
ff
ee ff
Add without Carry
A
←
(A) + (M)
–
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP
←
(SP) + (16
«
M)
H:X
←
(H:X) + (16
«
M)
– – – – – – IMM
– – – – – – IMM
IMM
DIR
EXT
IX2
– IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
Logical AND
A
←
(A) & (M)
0 – –
Arithmetic Shift Left
(Same as LSL)
C
b7
b0
0
– –
38 dd
48
58
68 ff
78
9E68 ff
37 dd
47
57
67 ff
77
9E67 ff
24
11
13
15
17
19
1B
1D
1F
25
27
90
92
28
29
22
rr
dd
dd
dd
dd
dd
dd
dd
dd
rr
rr
rr
rr
rr
rr
rr
Arithmetic Shift Right
b7
b0
C
– –
Branch if Carry Bit Clear
PC
←
(PC) + 2 + rel ? (C) = 0
– – – – – – REL
DIR (b0)
DIR (b1)
DIR (b2)
– – – – – – DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
– – – – – – REL
– – – – – – REL
– – – – – – REL
BCLR
n, opr
Clear Bit n in M
Mn
←
0
BCS
rel
BEQ
rel
BGE
opr
BGT
opr
BHCC
rel
BHCS
rel
BHI
rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
Branch if Greater Than or Equal To
(Signed Operands)
Branch if Greater Than (Signed
Operands)
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC
←
(PC) + 2 +
rel
? (C) = 1
PC
←
(PC) + 2 +
rel
? (Z) = 1
PC
←
(PC) + 2 +
rel
? (N
⊕
V)
= 0
PC
←
(PC) + 2 +
rel
? (Z) | (N
⊕
V)
= 0
– – – – – – REL
PC
←
(PC) + 2 +
rel
? (H) = 0
PC
←
(PC) + 2 +
rel
? (H) = 1
PC
←
(PC) + 2 +
rel
? (C) | (Z) = 0
– – – – – – REL
– – – – – – REL
– – – – – – REL
3
3
MC68HC908JL3E Family Data Sheet, Rev. 4
42
Freescale Semiconductor
Cycles
2
3
4
4
3
2
4
5
2
3
4
4
3
2
4
5
2
2
2
3
4
4
3
2
4
5
4
1
1
4
3
5
4
1
1
4
3
5
3
4
4
4
4
4
4
4
4
3
3
3
3
3
Effect
on CCR
Operand
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
