Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set Summary
Table 8-1. Instruction Set Summary (Sheet 5 of 8)
Effect on CCR
e
s
Source
Form
Operation
Description
o
d
e
V H I N Z C
M
C
O cp
d
JMP opr
DIR
EXT
IX2
IX1
IX
BC dd
2
3
4
3
2
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
CC hh ll
DC ee ff
EC ff
FC
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
–
–
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
ED ff
FD
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
↕ ↕ –
↕ ↕ –
↕ ↕ –
F6
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
DIR
45
55
ii jj
dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
2
3
4
4
3
2
4
5
FE
SP1
SP2
9EEE ff
9EDE ee ff
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
4
1
1
4
3
5
Logical Shift Left
(Same as ASL)
C
0
↕ –
–
–
↕ ↕ ↕
ff
b7
b0
SP1
9E68 ff
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
4
1
1
4
3
5
0
C
Logical Shift Right
↕ –
0
↕ ↕
ff
b7
b0
SP1
9E64 ff
dd
dd
dd
ii dd
dd
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E
5E
6E
7E
5
4
4
4
(M)Destination ← (M)Source
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
↕ ↕ –
H:X ← (H:X) + 1 (IX+D, DIX+)
MUL
Unsigned multiply
X:A ← (X) × (A)
–
–
0
INH
42
5
MC68HC908AS60 — Rev. 1.0
Technical Data
Central Processor Unit (CPU)
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