Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 8-1. Instruction Set Summary (Sheet 8 of 8)
Opcode
Source
Form
TST
opr
TSTA
TSTX
TST
opr,X
TST ,X
TST
opr,SP
TSX
Operation
Description
V H I N Z C
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
– –
↕
↕
DIR
INH
INH
–
IX1
IX
SP1
– INH
– INH
– INH
3D dd
4D
5D
6D ff
7D
9E6D ff
95
9F
94
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
H:X
←
(SP) + 1
A
←
(X)
(SP)
←
(H:X) – 1
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
–
–
–
– – –
– – –
– – –
–
–
–
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TXA
TXS
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
⊕
()
–( )
#
«
←
?
:
↕
—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
8.9 Opcode Map
The opcode map is provided in
Technical Data
Central Processor Unit (CPU)
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MC68HC908AS60 — Rev. 1.0
Cycles
3
1
1
3
2
4
2
1
2
Effect on CCR
Operand
Address
Mode
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