Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 8-1. Instruction Set Summary (Sheet 6 of 8)
Effect on CCR
e
s
Source
Form
Operation
Description
o
d
e
V H I N Z C
M
C
O cp
d
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
NEG opr,SP
SP1
9E60 ff
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
9D
1
3
A ← (A[3:0]:A[7:4])
62
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
INH
INH
INH
INH
87
8B
89
86
8A
88
2
2
2
2
2
2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
4
1
1
4
3
5
C
Rotate Left through Carry
Rotate Right through Carry
↕ –
–
↕ ↕ ↕
b7
b0
SP1
9E69 ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
4
1
1
4
3
5
C
↕ –
–
–
↕ ↕ ↕
ff
b7
b0
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ ↕ INH
80
81
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
–
–
–
–
–
–
INH
4
Technical Data
MC68HC908AS60 — Rev. 1.0
Central Processor Unit (CPU)
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