Low-Voltage Inhibit (LVI)
The LVI trip point selection bits, LVISEL[1:0], select the trip point
voltage, V , to be configured for 5V or 3.3V operation. The actual
TRIPF
trip points are shown in Section 23. Electrical Specifications.
Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever
the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0).
NOTE: After a power-on reset (POR) the user must configure the LVISEL[1:0}
bits for 3.3V or 5V operation before enabling the LVI module (by clearing
the LVIPWRD bit in CONFIG1 register).
NOTE: If the user requires 3.3V mode and enables the LVI module after
configuring the LVISEL[1;0] bits to 3.3V operation mode while the V
DD
supply is not above the V
for 3.3V mode, the MCU will immediately
TRIPF
go into reset. The LVI in this case will hold the MCU in reset until either
goes above the rising 3.3V trip point, V , which will release
V
DD
TRIPR
reset or V decreases to approximately 0V which will re-trigger the
DD
power-on reset.
LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the
configuration registers. See Section 5. Configuration Registers
(CONFIG) for details of the LVI’s configuration bits. Once an LVI reset
occurs, the MCU remains in reset until V rises above a voltage,
DD
V
, which causes the MCU to exit reset. See 9.4.2.5 Low-Voltage
TRIPR
Inhibit (LVI) Reset for details of the interaction between the SIM and the
LVI. The output of the comparator controls the state of the LVIOUT flag
in the LVI status register (LVISR). The LVIIE, LVIIF, and LVIIAK bits in
the LVISR control LVI interrupt functions.
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Technical Data
Low-Voltage Inhibit (LVI)
379
FREESCALE [ Freescale ]
