Low-Voltage Inhibit (LVI)
LVIIE — LVI Interrupt Enable Bit
This read/write bit enables the LVIIF bit to generate CPU interrupt
requests. Reset clears the LVIIE bit.
1 = LVIIF can generate CPU interrupt requests
0 = LVIIF cannot generate CPU interrupt requests
LVIIF — LVI Interrupt Flag
This clearable, read-only flag is set whenever the LVIOUT bit toggles.
Reset clears the LVIIF bit.
1 = LVIOUT has toggled
0 = LVIOUT has not toggled
LVIIAK — LVI Interrupt Acknowledge Bit
Writing a logic 1 to this write-only bit clears the LVI interrupt flag,
LVIIF. LVIIAK always reads as logic 0.
1 = Clears LVIIF bit
0 = No effect
21.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
21.6.1 Wait Mode
21.6.2 Stop Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets or interrupts, the LVI module can generate a reset or an
interrupt and bring the MCU out of wait mode.
If enabled in stop mode (LVISTOP = 1), the LVI module remains active
in stop mode. If enabled to generate resets or interrupts, the LVI module
can generate a reset or an interrupt and bring the MCU out of stop mode.
NOTE: If enabled to generate both resets and interrupts, there will be no LVI
interrupts, as resets have a higher priority.
Technical Data
382
MC68HC908LJ12 — Rev. 2.1
Low-Voltage Inhibit (LVI)
Freescale Semiconductor
FREESCALE [ Freescale ]
