Low-Voltage Inhibit (LVI)
21.4.1 Interrupt LVI Operation
In applications that can operate at V levels below the V
level,
TRIPF
DD
software can monitor V by polling the LVIOUT bit, or by setting the LVI
DD
interrupt enable bit, LVIIE, to enable interrupt requests. In the
configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0
to enable the LVI module, and the LVIRSTD bit must be at logic 1 to
disable LVI resets.
The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes
state (toggles). When LVIF is set, a CPU interrupt request is generated
if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF bit
can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit,
LVIIAK.
21.4.2 Forced Reset Operation
In applications that require V to remain above the V
level,
TRIPF
DD
enabling LVI resets allows the LVI module to reset the MCU when V
DD
falls below the V
level. In the configuration register 1 (CONFIG1),
TRIPF
the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI
module and to enable LVI resets.
If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI
reset has a higher priority over LVI interrupt. In this case, when V falls
DD
below the V
cleared.
level, an LVI reset will occur, and the LVIIE bit will be
TRIPF
21.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V fall below V
), the LVI
TRIPF
DD
will maintain a reset condition until V rises above the rising trip point
DD
voltage, V
. This prevents a condition in which the MCU is
TRIPR
continually entering and exiting reset if V is approximately equal to
DD
V
. V
is greater than V
by the hysteresis voltage, V
.
TRIPF
TRIPR
TRIPF
HYS
Technical Data
380
MC68HC908LJ12 — Rev. 2.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
FREESCALE [ Freescale ]
