Design Recommendations
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
MCF5274
MCF5275
MCF5274L
MCF5275L
Signal Name
GPIO
Alternate1 Alternate2 Dir.1
256 MAPBGA 196 MAPBGA
TEST
—
—
—
—
—
—
I
I
N9
N6
—
PLL_TEST
M14
Power Supplies
VDDPLL
VSSPLL
VSS
—
—
—
—
—
—
—
—
—
I
I
I
M15
K16
M13
L13
A1, A10, A16,
E5, E12, F6,
F11, G7:10,
H7:10, J1,
F7, F8, G6:9,
H6:9, J7, J8
J7:10, K7:10,
L6, L11, M5,
N16, R7, T1,
T16
OVDD
—
—
—
I
E6:8, F5, F7, F8, E5:7, F5, F6,
G5, G6, H5, H6, H10, J9, J10,
J11, J12, K11,
K12, L9, L10,
L12, M9:11
K8:10
VDD
—
—
—
—
—
—
I
I
D8, H13, K4, N8 D6, G5, G12, L7
SD_VDD
E9:11, F9, F10, E8:10, F9, F10,
F12, G11, G12, G10, H5, J5, J6,
H11, H12, J5,
J6, K5, K6, L5,
L7, L8, M6, M7,
M8
K5:7
1
2
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO
mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not
responsible for assigning these pins.
5
Design Recommendations
5.1
Layout
•
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF5275.
•
•
See application note AN1259 System Design and Layout Techniques for Noise Reduction in
MCU-Based Systems.
Match the PC layout trace width and routing to match trace length to operating frequency and board
impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the
PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
9
Preliminary—Subject to Change Without Notice
FREESCALE [ Freescale ]
