Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate1
Alternate2 Dir.
1
MCF5274
MCF5275
256 MAPBGA
E1, E2, F2
D1
B1, B2, A2
C2
MCF5274L
MCF5275L
196 MAPBGA
—
—
—
—
FEC1_TXD[3:1]
FEC1_TXER
FEC1_RXD[3:1]
FEC1_RXER
PFEC1L[7:5]
PFEC1L[4]
PFEC1L[3:1]
PFEC1L[0]
—
—
—
—
I
2
C
—
—
—
—
O
O
I
I
I2C_SDA
I2C_SCL
PFECI2C[1]
PFECI2C[0]
U2RXD
U2TXD
DMA
—
—
I/O
I/O
B10
C10
B7
A7
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
QSPI
QSPI_CS[3:2]
QSPI_CS1
QSPI_CS0
QSPI_CLK
QSPI_DIN
QSPI_DOUT
PQSPI[6:5]
PQSPI[4]
PQSPI[3]
PQSPI[2]
PQSPI[1]
PQSPI[0]
PWM[3:2]
—
—
I2C_SCL
I2C_SDA
—
DACK[3:2]
—
—
—
—
—
UARTs
U2RXD
U2TXD
U2CTS
U2RTS
U1RXD
U1TXD
U1CTS
U1RTS
U0RXD
U0TXD
U0CTS
PUARTH[3]
PUARTH[2]
PUARTH[1]
PUARTH[0]
PUARTL[7]
PUARTL[6]
PUARTL[5]
PUARTL[4]
PUARTL[3]
PUARTL[2]
PUARTL[1]
—
—
PWM1
PWM0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
O
I
O
I
O
I
O
I
O
I
O
O
O
O
I
O
—
—
R13, N12
T14
P12
T15
T13
R12
P10, N9
N10
M9
L11
M10
L10
T9
R9
P9
R8
A9
B9
C9
D9
A8
B8
C8
—
—
—
—
A6
D7
C7
B6
A4
A5
C6
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
