66-MHz Electrical Characteristics
Table G-8. Flash Module Life
Symbol
Array P/E Cycles
1
CENSOR Set/Clear
Cycles
2
Meaning
Maximum number of Program/Erase cycles per block to guarantee
data retention.
Minimum number of Program/Erase cycles per bit before failure.
Value
1,000
100
Min 15 years
3
Min 10 years
3
Array and CENSOR Data Minimum data retention at an average of 85 °C junction temperature.
Retention
Minimum data retention at an average of 125 °C junction temperature.
1
2
3
A Program/Erase cycle is defined as switching the bits from 1
to
0
to
1.
A CENSOR Set/Clear cycle is defined as switching the bits from 1
to
0
to
1.
Maximum total time @ 150 °C junction temperature
≤
1 year.
G.9
.
Power-Up/Down Sequencing
Table G-9. Power Supply Pin Groups
Symbol
V
DDH
(High Voltage Supply Group)
Types of Power Pins
Supply to the 5-V pads for output driver (V
DDH
)
Supply to the analog (QADC64E) circuitry (V
DDA
)
High voltage supply to the Flash module (V
FLASH
)
1
V
DDL
(Low Voltage Supply Pins)
Supply to low voltage pad drivers (QVDDL, NVDDL)
Supply to all low voltage internal logic (V
DD
)
Supply to low voltage Flash circuitry (V
DDF
)
1
Supply to system PLL
V
DDKA
(Low Voltage Keep-Alive
Supply Pins
2
Supply to IRAMSTBY
Supply to oscillator and other circuitry for keep-alive functions (KAPWR).
The supply symbols used in this section are described in
1
2
These power supplies are only available on the MPC563 and MPC564.
Any supply in the V
DDKA
group can be powered with the V
DDL
if the function which it supplies is not required during
“Keep-alive.”
MPC561/MPC563 Reference Manual, Rev. 1.2
G-12
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
