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MPC563MZP66 参数 Datasheet PDF下载

MPC563MZP66图片预览
型号: MPC563MZP66
PDF下载: 下载PDF文件 查看货源
内容描述: 参考手册 [Reference Manual]
分类和应用: 外围集成电路时钟
文件页数/大小: 1420 页 / 10582 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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66-MHz Electrical Characteristics
There are two power-up/down options. Choosing which one is required for an application will depend
upon circuitry connected to 2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Power-up/down
option A is required if 2.6-V compliant pins and dual 2.6-V/5-V compliant pins are connected to the 5-V
supply with a pull-up resistor or driven by 5-V logic during power-up/down. In applications for which this
scenario is not true the power-up/down option B may be implemented. Option B is less stringent and easier
to ensure over a variety of applications.
Refer to
for a list of 2.6 V and dual 2.6V/5 V compliant pins.
The power consumption during power-up/down sequencing will stay below the operating power
consumption specifications when following these guidelines.
NOTE:
The V
DDH
ramp voltage should be kept below 50V/ms and the V
DDL
ramp
rate less that 25V/ms.
G.9.1
Power-Up/Down Option A
The Option A power-up sequence (excluding V
DDKA
) is
1. V
DDH
V
DDL
+ 3.1 V (V
DDH
cannot lead V
DDL
by more than 3.1 V)
2. V
DDH
V
DDL
- 0.5 V (V
DDH
cannot lag V
DDL
by more than 0.5 V)
The first step in the sequence is required is due to gate-to-drain stress limits for transistors in the pads of
2.6-V compliant pins and dual 2.6-V/5-V compliant pins. Damage can occur if gate-to-drain voltage
potential is greater than 3.1 V. This is only a concern at power-up/down. The second step in the sequence
is required is due to ESD diodes in the pad logic for dual 2.6-V/5-V compliant pins and 2.6-V pins. The
diodes are forward biased when V
DDL
is greater than V
DDH
and will start to conduct current.
illustrates the power-up sequence if no keep-alive supply is required.
illustrates the
power-up sequence if a keep-alive supply is required. The keep-alive supply should be powered-up at the
same instant or before both the high voltage and low voltage supplies are powered-up.
V
DDH
3.1-V lead
V
DDL
0.5-V lag
V
DDH
cannot lead V
DDL
by more than 3.1 V
V
DDH
cannot lag V
DDL
by more than 0.5 V
Figure G-1. Option A Power-Up Sequence Without Keep-Alive Supply
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-13