66-MHz Electrical Characteristics
V
DDH
V
DDH
≤
5.25V
V
DDL
0.5-V lag
V
DDH
cannot lead V
DDL
by more than 0.5V
Ramp down rates may
differ with load.
Figure G-7. Option B Power-Down Sequence Without Keep-Alive Supply
V
DDH
V
DDL
V
DDKAP
0.5-V lag
Ramp down rates may
differ with load.
V
DDH
cannot lead V
DDL
by more than 0.5V
Figure G-8. Option B Power-Down Sequence with Keep-Alive Supply
G.10 Issues Regarding Power Sequence
G.10.1
Application of PORESET or HRESET
When V
DDH
is rising and V
DDL
is at 0.0 V, as V
DDH
reaches 1.6 V, all 5 V drivers are tristated. Before
V
DDH
reaches 1.6V, all 5 V outputs are unknown. If V
DDL
is rising and V
DDH
is at least 3.1V greater than
V
DDL
, then the 5 V drivers can come out of tristate when V
DDL
reaches 1.1V, and the 2.6 V drivers can
start driving when V
DDL
reaches 0.5 V. For these reasons, the PORESET or HRESET signal must be
asserted during power-up before V
DDL
is above 0.5 V.
If the PORESET or HRESET signal is not asserted before this condition, there is a possibility of disturbing
the programmed state of the flash. In addition, the state of the pads are indeterminant until PORESET or
HRESET propagates through the device to initialize all circuitry.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-17
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
