CPM Electrical Characteristics
SPICLK
(CI = 0)
(Output)
161
161
SPICLK
(CI = 1)
(Output)
163
162
SPIMISO
(Input)
msb
166
Data
165
167
SPIMOSI
(Output)
msb
Data
lsb
lsb
164
166
msb
msb
167
167
160
166
Figure 66. SPI Master (CP = 1) Timing Diagram
11.11 SPI Slave AC Electrical Specifications
provides the SPI slave timings as shown in
and
Table 25. SPI Slave Timing
All Frequencies
Num
Characteristic
Min
170
171
172
173
174
175
176
177
Slave cycle time
Slave enable lead time
Slave enable lag time
Slave clock (SPICLK) high or low time
Slave sequential transfer delay (does not require deselect)
Slave data setup time (inputs)
Slave data hold time (inputs)
Slave access time
2
15
15
1
1
20
20
—
Max
—
—
—
—
—
—
—
50
t
cyc
ns
ns
t
cyc
t
cyc
ns
ns
ns
Unit
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
62
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
