MB15F72SP
s
PIN DESCRIPTION
Pin no.
TSSOP BCC
1
2
3
4
5
6
19
20
1
2
3
4
Pin name I/O
OSC
IN
GND
fin
IF
Xfin
IF
GND
IF
V
CCIF
I
Descriptions
The programmable reference divider input. TCXO should be connected with a
AC coupling capacitor.
Ground for OSC input buffer and the shift register circuit.
I
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section(except for the charge
pump circuit), the OSC input buffer and the shift register circuit.
When power is OFF, latched data of IF-PLL is lost.
I
Power saving mode control for the IF-PLL section. This pin must be set at “L”
Power-ON. (Open is prohibited.)
PS
IF
= “H” ; Normal mode / PS
IF
= “L” ; Power saving mode
7
8
9
5
6
7
PS
IF
Vp
IF
D
OIF
Power supply voltage input pin for the IF-PLL charge pump.
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FCbit.
Lock detect signal output (LD)/phase comparator monitoring
output (fout).The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
Charge pump output for the RF-PLL section.
Phase characterstics of the phase detector can be reversed by FCbitt.
10
8
LD/fout
O
11
12
13
9
10
11
D
ORF
Vp
RF
PS
RF
O
Power supply voltage input pin for the RF-PLL charge pump.
I
Power saving mode control for the RF-PLL section. This pin must be set at “L”
Power-ON. (Open is prohibited.)
PS
RF
= “H” ; Normal mode / PS
RF
= “L” ; Power saving mode
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit).
14
15
16
17
12
13
14
15
V
CCRF
GND
RF
Xfin
RF
fin
RF
Ground for the RF-PLL section.
I
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input(with the schmitt trigger circuit).
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in a serial data.
Serial data input(with the schmitt trigger circuit).
A data is transferred to the corresponding latch(IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
Clock input for the 23-bit shift register (with the schmitt trigger circuit).
One bit of data is shifted into the shift register on a rising edge of the clock.
3
18
16
LE
I
19
17
Data
I
20
18
Clock
I
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
