GS4901B/GS4900B Preliminary Data Sheet
Table 2-2: AC Electrical Characteristics (Continued)
V
DD
= 1.8V, T
A
= 0°C to 70°C, unless otherwise specified.
Parameter
GSPI Input Hold Time
Symbol
t
8
in
Condition
–
Min
1.5
Typ
–
Max
–
Units
ns
Notes
6
NOTES
1. The video output clock may be directly connected to Gennum’s GS9062 serializer for a SMPTE-compliant SDI output with output jitter
below 0.2UI.
2. All output standards EXCEPT VID_STD[5:0] = 1 (450ps typ.) and VID_STD[5:0] = 5 or 6 (500ps typ.)
3. Timings from any CLK output to any other CLK output.
4. If fs=96kHz and ACLK is configured to output a clock signal at 192fs or 384fs, a 512fs clock will typically have a 33% duty cycle distortion.
See
5. With PCLK phasing delay set to nominal (zero offset), each increment of the clock phasing adjustment decreases output hold time and
delay time by a nominal 700ps. The times t
OD
and t
OH
are defined in
6. For detailed GSPI timing parameters, please refer to
t
OH
t
OD
PCLK
50%
V
OH
TIMING_OUT
V
OH
V
OL
V
OL
Figure 2-1: PCLK to TIMING_OUT Signal Output Timing
Table 2-3: Suggested External Crystal Specification
27.000000 MHz
AT Cut
Nominal Dissipation = 50 uW
Frequency accuracy at 25°C = +/- 10ppm
Frequency variation 0-70°C = +/- 10ppm
ASR = 50 +/- 20Ω
NOTE: The user may select an appropriate crystal accuracy for their application. If the device is
operating in Free Run mode, the output clock and timing signals will have the same accuracy as
the crystal. However, if operating in Genlock mode, all output signals are based on the input
reference, and therefore a less accurate crystal may be sufficient. See
37703 - 0
April 2006
32 of 95
GENNUM [ GENNUM CORPORATION ]
