GS8161FZ18BD 参数 Datasheet PDF下载

GS8161FZ18/32/36BD

GS8161FZ18/32/36BD 165-Bump BGA Pin Description

Symbol

A

0

, A

1

A

DQ

A

DQ

B

DQ

C

DQ

D

B

A

, B

B

, B

C

, B

D

NC

CK

CKE

W

E

1

E

3

E

2

G

ADV

ZZ

LBO

TMS

TDI

TDO

TCK

MCH

V

DD

V

SS

V

DDQ

Type

I

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

I

O

I

—

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQ

A

, DQ

B

, DQ

C

, DQ

D

I/Os; active low

No Connect

Clock Input Signal; active high

Clock Input Buffer Enable; active low

Write Enable; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active high

Sleep mode control; active high

Linear Burst Order mode; active low

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Must Connect High

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.00 6/2006

5/28

© 2006, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.