GS816272C-200I 参数 Datasheet PDF下载

GS816272C

GS816272 BGA Pin Description

Symbol

A

0

, A

1

An

DQ

A

DQ

B

DQ

C

DQ

D

DQ

E

DQ

F

DQ

G

DQ

H

B

A

, B

B

, B

C

,B

D,

B

E

, B

F

, B

G

,B

H

NC

CK

GW

E

1,

E

3

E

2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

SCD

MCH

MCL

BW

ZQ

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

I

I

I

I

O

I

I

I

I

Type

I

I

Description

Address field LSBs and Address Counter Preset Inputs.

Address Inputs

I/O

Data Input and Output pins

I

—

I

I

I

I

I

I

I

I

I

I

I

I

Byte Write Enable for DQ

A

, DQ

B

, DQ

C

, DQ

D,

DQ

E

,

DQ

F

, DQ

G

, DQ

H

I/Os; active low

No Connect

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Single Cycle Deselect/Dual Cycle Deselect Mode Control

Must Connect High

Must Connect Low

Byte Enable; active low

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 2.18 11/2005

3/31

© 1999, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.