GS816272C
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
Pin Name
LBO
FT
ZZ
SCD
ZQ
State
L
H
L
H or NC
L or NC
H
L
H or NC
L
H or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the ZQ, SCD, and FT pinsand a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.18 11/2005
4/31
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
