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GS816036T-133I 参数 Datasheet PDF下载

GS816036T-133I图片预览
型号: GS816036T-133I
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×18 , 512K ×32 , 512K ×36 18MB同步突发静态存储器 [1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs]
分类和应用: 存储静态存储器
文件页数/大小: 28 页 / 811 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary
GS816018/32/36T-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter
3.3 V Supply Voltage
2.5 V Supply Voltage
3.3 V V
DDQ
I/O Supply Voltage
2.5 V V
DDQ
I/O Supply Voltage
Symbol
V
DD3
V
DD2
V
DDQ3
V
DDQ2
Min.
3.0
2.3
3.0
2.3
Typ.
3.3
2.5
3.3
2.5
Max.
3.6
2.7
3.6
2.7
Unit
V
V
V
V
Notes
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be
–2
V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
DDQ3
Range Logic Levels
Parameter
V
DD
Input High Voltage
V
DD
Input Low Voltage
V
DDQ
I/O Input High Voltage
V
DDQ
I/O Input Low Voltage
Symbol
V
IH
V
IL
V
IHQ
V
ILQ
Min.
2.0
–0.3
2.0
–0.3
Typ.
Max.
V
DD
+ 0.3
0.8
V
DDQ
+ 0.3
0.8
Unit
V
V
V
V
Notes
1
1
1,3
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be
–2
V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
V
DDQ2
Range Logic Levels
Parameter
V
DD
Input High Voltage
V
DD
Input Low Voltage
V
DDQ
I/O Input High Voltage
V
DDQ
I/O Input Low Voltage
Symbol
V
IH
V
IL
V
IHQ
V
ILQ
Min.
0.6*V
DD
–0.3
0.6*V
DD
–0.3
Typ.
Max.
V
DD
+ 0.3
0.3*V
DD
V
DDQ
+ 0.3
0.3*V
DD
Unit
V
V
V
V
Notes
1
1
1,3
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be
–2
V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. V
IHQ
(max) is voltage on V
DDQ
pins plus 0.3 V.
Rev: 2.12 3/2002
13/28
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.