GS882ZV36BB-300I 参数 Datasheet PDF下载

GS882ZV18/36BB/D-333/300/250/200

GS882ZV18/36B BGA Pin Description

Symbol

A

0

, A

1

A

DQ

A

DQ

B

DQ

C

DQ

D

B

A

, B

B

, B

C

, B

D

NC

CK

CKE

W

E

1

E

3

E

2

G

ADV

ZZ

FT

LBO

PE

ZQ

TMS

TDI

TDO

TCK

MCH

DNU

V

DD

V

SS

V

DDQ

Type

I

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

—

—

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQ

A

, DQ

B

, DQ

C

, DQ

D

I/Os; active low

No Connect

Clock Input Signal; active high

Clock Enable; active low

Write Enable; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active high

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

9th Bit Enable; active low (119-bump BGA only)

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Must Connect High

Do Not Use

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.03 3/2005

6/33

© 2004, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.