ISSUED DATE :2006/06/14
REVISED DATE :
V
CC
=+1.8 ~ 5.5V, C
L
=1 TTL Gate & 100pF
(unless otherwise noted)
Symbol
Test Condition
Parameter
V
CC
=1.8V
Clock Frequency, SCL
f
SCL
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Clock Pulse Width Low
t
LOW
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Clock Pulse Width High
t
HIGH
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Noise Suppression Time
(1)
t
I
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Clock Low to Data Out Valid
t
AA
V
CC
=2.7 ~ 5.5V
Time the bus must be free before
V
CC
=1.8V
t
BUF
a new transmission can start
(1)
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Start Hold Time
t
HD.STA
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Start Setup Time
t
SU.STA
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Data in Hold Time
t
HD.DAT
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Data in Setup Time
t
US.DAT
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Input Rise Time
(1)
t
R
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Input Fall Time
(1)
t
F
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Stop Setup Time
t
SU.STO
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Data Out Hold Time
t
DH
V
CC
=2.7 ~ 5.5V
V
CC
=1.8V
Write Cycle Time
t
WR
V
CC
=2.7 ~ 5.5V
Endurance V
CC
=1.8V
5.0V, 25 : , Byte Mode
(1)
V
CC
=2.7 ~ 5.5V
Note: 1. This parameter is characterized and not 100% tested.
AC Characteristics
Applicable over recommended operating range from: T
A
=-40 ~ +85 : ,
Min
-
4.7
1.2
4.0
0.6
-
0.1
0.1
4.7
1.2
4.0
0.6
4.7
0.6
0
0
200
100
-
-
4.7
0.6
100
50
-
1M
1M
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
400
-
-
100
50
4.5
0.9
-
-
-
-
-
1.0
0.3
300
300
-
-
5
5
-
Unit
KHz
s
s
ns
s
s
s
s
s
ns
s
ns
s
ns
ms
Write
Cycles
Device Operation
Clock and Data Transitions:
Transitions on the SDA pin should only occur when SCL is low (refer to the Data
Validity timing diagram in Figure 5). If the SDA pin changes when SCL is high, then the transition will be
interpreted as a START or STOP condition.
START Condition:
A START condition occurs when the SDA transitions form high to low when SCL is high.
The START signal is usually used to initiate a command (refer to the Start and Stop Definition timing diagram in
Figure 6).
STOP Condition:
A STOP condition occurs when the SDA transitions form low to high when SCL is high (refer
to Figure 6. START and STOP Definition timing diagram). The STOP command will put the device into standby
mode after no acknowledgment is issued during the read sequence.
Acknowledge:
An acknowledgement is sent by pulling the SDA low to confirm that a word has been
successfully received. All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words, so acknowledgments are usually issued during the 9
th
clock cycle.
Standby Mode:
Standby mode is entered when the chip is initially powered-on or after a STOP command has
been issued and any internal operations have been completed. .
Memory Reset:
In the event of unexpected power or connection loss, a START condition can be issued to
restart the input command sequence. If the device is currently in write cycle mode, this command will be
ignored.
GSC24BC01/02/02/04/08/16
Page: 4/9
GTM [ GTM CORPORATION ]
