HANBit
HMN1M8D
POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V)
PARAMETER
VCC slew, 4.75 to 4.25V
VCC slew, 4.75 to VSO
SYMBOL
CONDITIONS
MIN
300
10
TYP.
MAX
UNIT
㎲
tPF
tFS
-
-
-
-
㎲
㎲
VCC slew, VSO to VPFD (max)
tPU
tCER
tDR
0
40
5
-
80
-
-
Time during which SRAM
is write-protected after VCC
passes VPFD on power-up.
Chip enable recovery time
120
-
ms
years
㎲
Data-retention time in
Absence of VCC
TA = 25℃
Delay after Vcc slews down
past VPFD before SRAM is
Write-protected.
Write-protect time
tWPT
40
100
150
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*1,2
tRC
Address
tACC
tOH
Previous Data Valid
DOUT
Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
tRC
/CE
tACE
tCHZ
tCLZ
DOUT
High-Z
High-Z
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
6
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
