HANBit
HMN1M8D
- WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5
Address
tAW
tWR2
tAS
tCW
/CE
tWP
/WE
tDH2
tDW
Data-in
DIN
tWZ
DOUT
High-Z
Data
Undefined
NOTE: 1. /CE or /WE must be high during address transition.
2. Because I/O may be active (/OE low) during this period, data input signals of opposite
polarity to the outputs must not be applied.
3. If /OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
POWER-DOWN/POWER-UP TIMING
VCC
tPF
4.75
VPFD
VPFD
4.25
VSO
VSO
tFS
tPU
tCER
tDR
tWPT
/CE
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
8
HANBit Electronics Co.,Ltd