HANBit
Setting the Clock
HMNR328D(V)
Bit D7 of the Control Register (7FF8h) is the WRITE Bit. Setting the WRITE Bit to a
’
like the READ Bit, halts updates to
1,’
the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD
format. Resetting the WRITE Bit to a
’
then transfers the
0’
values of all time registers (7FFh -7FF9h, 7FF1h) to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next clock update will occur approximately one second later.
Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to
’
0.’
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the
oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds
Register (7FF9h). Setting it to a
’
stops the oscillator. When reset to a
’
the HMNR328D oscillator starts within one
1’
0,’
second.
Note
: It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST).
Calibrating the Clock
The HMNR328D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are
factory calibrated at 25° C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator
frequency error at 25° C, which equates to about
±
1.53 minutes per month. When the Calibration circuit is properly
employed, accuracy improves to better than +1/-2 ppm at 25° C. The oscillation rate of crystals changes with temperature.
The HMNR328D design employs periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative
calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the
Control Register.
Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower
order bits (D4-D0) in the Control Register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary
form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle
will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or -
2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which
corresponds to a total range of +5.5 or -2.75 minutes per month. One method for ascertaining how much calibration a
given HMNR328D(V) may require involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is packaged in a nonuser serviceable
enclosure. The designer could provide a simple utility that accesses the Calibration bits.
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Rev. 0.0 (January, 2002)
11
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