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HMNR328DV-85I 参数 Datasheet PDF下载

HMNR328DV-85I图片预览
型号: HMNR328DV-85I
PDF下载: 下载PDF文件 查看货源
内容描述: 5.0或3.3V , 256K位( 32千位×8 ) TIMEKEEPER NVSRAM [5.0 or 3.3V, 256K bit (32 Kbit x 8) TIMEKEEPER NVSRAM]
分类和应用: 静态存储器
文件页数/大小: 13 页 / 302 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
WRITE Mode
HMNR328D(V)
The HMNR328D(V) is in the WRITE Mode whenever /WE (WRITE Enable) and /CE (Chip Enable) are low state after the
address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of /WE or /CE. A
WRITE is terminated by the earlier rising edge of /WE or /CE. The addresses must be held valid throughout the cycle. /CE
or /WE must return high for a minimum of t
EHAX
from Chip Enable or t
WHAX
from WRITE Enable prior to the initiation of
another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the end of WRITE and remain valid for t
WHDX
afterward.
/OE should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on /CE and /OE a low on /WE will disable the outputs t
WLQZ
after /WE falls.
WRITE AC Waveforms, WRITE Enable Controlled
A0-A14
WRITE AC Waveforms, Chip Enable Controlled
A0-A14
URL : www.hbe.co.kr
Rev. 0.0 (January, 2002)
7
HANBit Electronics Co.,Ltd.