HANBit
HSD32M64D8KP
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-75
PARAMETER
CLK cycle time
CLK to valid
output delay
Output data
hold time
CAS latency=3
CAS latency=3
CAS latency=3
SYMBOL
MIN
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
3
2.5
2.5
1.5
0.8
1
5.4
7.5
MAX
1000
5.4
3
3
3
2
1
1
6
MIN
10
MAX
1000
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1,2
2
3
3
3
3
3
2
-10L
UNIT
NOTE
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
CAS latency=3
in Hi-Z
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Entry
Refresh
Self
refres
h
Exit
CKE
n-1
H
H
CKE
n
X
H
L
H
H
Bank active & row address.
Auto
precharge
disable
Auto
precharge
disable
Auto
precharge
disable
H
X
L
X
L
X
H
X
H
X
V
Row address
/C
S
L
L
L
L
/R
A
S
L
L
H
/C
A
S
L
L
H
/W
E
L
H
H
X
X
3
D
Q
M
X
X
BA
0,1
A10/
AP
OP code
X
A11
A9~A0
NOTE
1,2
3
3
3
Read &
column
address
Write &
column
L
H
X
L
H
L
H
X
V
H
H
X
L
H
L
L
X
V
L
Column
Address
(A0 ~ A9)
Column
Address
4
4,5
4
URL:www.hbe.co.kr
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7
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HANBiT Electronics Co., Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
