HANBit
HSD8M32B4
+3.3V
V
tt
=1.4V
1200Ω
D
OUT
870Ω
50pF*
D
OUT
50Ω
Z0=50Ω
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
(
Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
SYMBOL
-13
t
RRD
(min)
t
RP
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
tRC
(min)
UNIT
-12
16
20
20
48
100
65
68
2
2 CLK + 20 ns
1
1
1
2
ea
CLK
CLK
CLK
70
70
-10
20
20
20
50
-10L
20
20
20
50
ns
ns
ns
ns
ns
ns
CLK
15
20
20
45
NOTE
1
1
1
1
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
1
2.5
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
-
2
2
3
4
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
URL:www.hbe.co.kr
REV.1.0 (August.2002).
- 7
-
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
