HM514170C, HM51S4170C Series
Self refresh Mode
HM51S4170C
-7
Parameter
RAS
pulse width (self refresh)
RAS
precharge time (self refresh)
CAS
hold time (self refresh)
Symbol Min
t
RASS
t
RPS
t
CHS
100
130
–50
Max
—
—
—
-8
Min
100
150
–50
Max
—
—
—
Unit
µs
ns
ns
Notes
23, 24,
25
Notes: 1. AC measurements assume t
T
= 5 ns.
2. Assumes that t
RCD
≤
t
RCD
(max) and t
RAD
≤
t
RAD
(max). If t
RCD
or t
RAD
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that t
RCD
≥
t
RCD
(max) and t
RAD
≤
t
RAD
(max).
5. Assumes that t
RCD
≤
t
RCD
(max) and t
RAD
≥
t
RAD
(max).
6. t
OFF
(max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between V
IH
and V
IL
.
8. Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is specified as
a reference point only, if t
RCD
is greater than the specified t
RCD
(max) limit, then access time is
controlled exclusively by t
CAC
.
9. Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is specified as
a reference point only, if t
RAD
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
10. t
WCS
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only: if t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and
the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min), t
AWD
≥
t
AWD
(min) and t
CPW
≥
t
CPW
(min), the cycle is a read-modify-
write and the data output will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
11. These parameters are referred to
CAS
leading edge in an early write cycle and to
WE
leading
edge in a delayed write or a read-modify-write cycle.
12. t
RASC
defines
RAS
pulse width in fast page mode cycles.
13. Access time is determined by the longer of t
AA
or t
CAC
or t
ACP
.
14. After power up pause for 100
µs,
then DRAM initialization requires a minimum of eight
RAS
only refresh or eight
CAS-before-RAS
refresh cycles. If the user will implement
CAS-before-
RAS
timing in their system, then the eight initialization cycles MUST be
CAS-before-RAS
cycles
15. In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying
data to the device.
16. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
17. The supply voltage with all V
CC
pins must be on the same level. The supply voltage with all V
SS
pins must be on the same level.
18. A word of data can be written only when
UWE
and
LWE
go low at the same time. This implies
that early write cycles cannot be combined with delayed write cycles in the same cycles
because all data is latched at the fall of the first
WE.
In other words, staggering the
WE
signals
in one cycle is not permitted.
19. t
RCH
, t
RRH
, t
WCS
, t
RWD
, t
CWD
and t
AWD
are determined by the earlier falling edge of
UWE
and
LWE.
20. t
WCH
and t
RCS
are determined by the later rising edge of
UWE
or
LWE.
21. t
WP
, t
RWL
, t
CWL
, t
OEH
, t
DS
, t
DH
and t
CPW
should be satisfied by both
UWE
and
LWE.
11
HITACHI [ HITACHI SEMICONDUCTOR ]
