HM514170C, HM51S4170C Series
22. When out put buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC
/V
SS
line noise, which causes to degrade V
IH
(min)/V
IL
(max) level.
23. If you use distributed CBR refresh mode with 15.6
µs
interval in normal read/write cycle, CBR
refresh should be executed within 15.6
µs
immediately after exiting from and before entering
into self refresh mode.
24. If you use
RAS
only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles
of distributed CBR refresh with 15.6
µs
interval should be executed within 16 ms immediately
after exiting from and before entering into the self refresh mode.
25. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh
mode again.
26.
H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
Invalid Dout
12
HITACHI [ HITACHI SEMICONDUCTOR ]
