GM71C18163C
GM71CS18163CL
Recommended DC Operating Conditions (TA = 0 ~ +70C)
Symbol
VCC
Parameter
Min
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
5.0
VIH
Input High Voltage
Input Low Voltage
2.4
-
-
6.0
V
VIL
-1.0
0.8
V
Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
Truth Table
Output
Open
Operation
RAS
H
LCAS UCAS
WE
D
OE
D
Notes
D
L
H
L
L
H
L
D
H
L
L
H
L
L
H
L
L
H
1,3
Standby
L
H
L
Valid
Lower byte
L
1,3
L
H
Valid
Read cycle
Upper byte
L
Valid
H
L
L
L
L
L
L
L
Word
D
L
Open
Lower byte
L
Open
Early write cycle
D
D
H
H
H
Upper byte
1,2,3
1,2,3
1,3
L
Open
Word
L
Undefined
Undefined
L
Lower byte
Upper byte
Delayed Write
cycle
H
L
L
L
Undefined
Valid
Word
Lower byte
L
L
L
H to L L to H
H to L L to H
H to L L to H
Read-modify
-write cycle
H
L
L
Upper byte
Valid
L
H
L
L
L
Valid
Open
Word
Word
D
D
D
D
D
D
H to L
H to L
H to L
L
CBR Refresh
or
Self Refresh
(L-series)
H
Open
Open
Word
Word
1,3
L
RAS-only
Refresh cycle
Open
Open
Word
H
L
H
D
H
D
H
L
L
1,3
1,3
Read cycle
(Output disabled)
L
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2. tWCS >= 0ns Early write cycle
tWCS <= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’01
HYNIX [ HYNIX SEMICONDUCTOR ]
