HY57V283220(L)T(P) / HY5V22(L)F(P)
COMMAND TRUTH TABLE
Command
Mode Register Set
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
DQM
Auto Refresh
Burst-Read-Single-WRITE
Entry
Self Refresh
1
Exit
CKEn-1
H
H
H
H
CKEn
X
X
X
X
CS
L
H
L
L
L
RAS
L
X
H
L
H
CAS
L
X
H
H
L
WE
L
X
H
H
H
DQM
X
X
X
X
CA
RA
L
H
L
H
H
L
X
X
X
A9 Pin High
(Other Pins OP code)
3
ADDR
A10/
AP
OP code
X
BA
Note
V
V
H
X
L
H
L
L
X
CA
V
X
V
H
H
H
H
H
H
L
X
X
L
L
L
H
X
H
H
L
L
X
X
V
X
H
X
L
H
L
L
L
H
L
H
L
H
L
H
L
L
L
L
X
H
X
H
X
H
X
V
X
L
L
L
X
H
X
H
X
H
X
V
H
L
H
X
H
X
H
X
H
X
V
X
X
X
X
X
Entry
Precharge power
down
Exit
H
L
X
X
X
L
H
Clock
Suspend
Entry
Exit
H
L
L
H
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.9 / July 2004
13
HYNIX [ HYNIX SEMICONDUCTOR ]
