HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-5
Parameter
Symbol
Min
CAS Latency = 3
CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
5
1000
10
2
2
-
-
1.5
1.5
1
1.5
1
1.5
1
1.5
1
1
-
-
-
-
4.5
6
-
-
-
-
-
-
-
-
-
-
4.5
6
10
Max
-55
Min
5.5
1000
10
-
-
5
6
-
-
-
-
-
-
-
-
-
-
5
6
2.5
2.5
-
-
2
1.5
1
1.5
1
1.5
1
1.5
1
1
-
-
Max
Min
6
-6
Max
Min
7
1000
10
-
-
5.5
6
-
-
-
-
-
-
-
-
-
-
5.5
6
3
3
-
-
2
1.75
1
1.75
1
1.75
1
1.75
1
1
-
-
-7
Max
-H
Min
7.5
Max
Min
8
1000
10
-
-
5.5
6
-
-
-
-
-
-
-
-
-
-
5.5
6
3
3
-
-
2
1.75
1
1.75
1
1.75
1
1.75
1
1
-
-
-
-
5.5
6
-
-
-
-
-
-
-
-
-
-
5.5
6
-10
3
3
-
-
2
2
1
2
1
2
1
2
1
1
-
-
-8
Max
Min
10
1000
10
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
3
3
-
-
2
2
1
2
1
2
1
2
1
1
-
-
-P
Max
Min
10
1000
12
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
3
3
-
-
2
2
1
2
1
2
1
2
1
1
-
-
-S
Unit Note
Max
ns
1000
ns
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
ns
ns
ns
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
1
1
1
1
1
1
1
1
1
1
System clock
cycle time
1000
Clock high pulse width
Clock low pulse width
CAS Latency = 3
CAS Latency = 2
2.25
2.25
-
-
2
1.5
1
1.5
1
1.5
1
1.5
1
1
-
-
Access time from
clock
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
CAS Latency = 3
CAS Latency = 2
CLK to data output
in high Z-time
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.9 / July 2004
9
HYNIX [ HYNIX SEMICONDUCTOR ]
