HY57V641620HG
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-5I
Parameter
Symbol
Min
CAS Latency =
tCK3
3
CAS Latency =
tCK2
2
tCHW
tCLW
5
1000
10
1.75
1.75
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
4.5
6
-
-
-
-
-
-
-
-
-
-
10
2
2
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
5
6
-
-
-
-
-
-
-
-
-
-
Max
Min
5.5
1000
10
2
2
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
Max
Min Max
6
100
0
10
2.5
2.5
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
Min
7
1000
7.5
2.5
2.5
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
5.4
5.4
-
-
-
-
-
-
-
-
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
Max
Min
7.5
1000
10
2.5
2.5
-
-
5.4
6
-
-
-
-
-
-
-
-
-
-
Max
Min
7.5
1000
10
3
3
-
-
2.0
2
1
2
1
2
1
2
1
1
3
5.4
CAS Latency =
tOHZ2
2
5.4
5.4
5.4
5.4
5.4
3
6
-
-
6
6
-
-
-
-
-
-
-
-
-
-
6
6
6
ns
-
2.0
2
1
2
1
2
1
2
1
1
Max
Min
8
1000
10
3
3
-
-
6
6
-
-
-
-
-
-
-
-
-
-
Max
Min
10
1000
12
3
3
-
-
2.0
2
1
2
1
2
1
2
1
2
-
-
6
8
-
-
-
-
-
-
-
-
-
-
Max
Min
10
1000
ns
ns
ns
ns
2
CAS Latency =
tAC2
2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Max
ns
-55I
-6I
-7I
-KI
-HI
-8I
-PI
-SI
Unit
Note
System clock
cycle time
Clock high pulse width
Clock low pulse width
Access time
from clock
CAS Latency =
tAC3
3
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time tOLZ
CAS Latency =
tOHZ3
3
CLK to data
output in high
Z-time
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.0/Jan. 02
7
HYNIX [ HYNIX SEMICONDUCTOR ]
