Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
11
Preliminary
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Parameter
CAS
Latency=3
CAS
Latency=2
Symbol
t
CK3
t
CK2
t
CHW
t
CLW
t
AC3
t
AC2
t
OH
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CS
t
CH
5
6
7
H
P
Unit Note
Min Max Min Max Min Max Min Max Min Max
5.0
1000
10
2.0
2.0
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
-
-
-
-
4.5
6.0
-
-
-
-
-
-
-
-
-
-
4.5
6.0
10
2.5
2.5
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
-
-
-
-
5.5
6.0
-
-
-
-
-
-
-
-
-
-
5.5
6.0
6.0
1000
10
3.0
3.0
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
-
-
5.5
6.0
-
-
-
-
-
-
-
-
-
-
5.5
6.0
7.0
1000
10
3.0
3.0
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
-
-
5.5
6.0
-
-
-
-
-
-
-
-
-
-
6.0
6.0
7.5
1000
10
3.0
3.0
-
-
2.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
-
-
-
-
5.5
6.0
-
-
-
-
-
-
-
-
-
-
6.0
6.0
10
1000
System Clock
Cycle Time
ns
ns
ns
ns
ns
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
Clock High Pulse Width
Clock Low Pulse Width
Access Time
From Clock
CAS
Latency=3
CAS
Latency=2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z
t
OLZ
Time
CLK to
Data Output
in High-Z Time
CAS
Latency=3
CAS
Latency=2
t
OHZ3
t
OHZ2
Note :
1. Assume t
R
/ t
F
(input rise and fall time) is 1ns. If t
R
& t
F
> 1ns, then [(t
R
+t
F
)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If t
R
> 1ns,
then (t
R
/2-0.5)ns should be added to the parameter.
Rev. 0.2 / June. 2005
9
HYNIX [ HYNIX SEMICONDUCTOR ]
