Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY5V66E(L)F6(P) Series
11
Preliminary
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh
logic & timer
Internal Row
Counter
CLK
CKE
State Machine
Row Active
1Mx16 BANK 3
Row
Pre
Decoder
1Mx16 BANK 2
1Mx16 BANK 1
1Mx16 BANK 0
DQ0
I/O Buffer & Logic
Sense AMP & I/O Gate
X-Decoder
X-Decoder
X-Decoder
X-Decoder
CS
RAS
CAS
Refresh
Memory
Cell
Array
Column Active
WE
U/LDQM
Column
Pre
Decoder
DQ15
Y-Decoder
Bank Select
Column Add
Counter
A0
A1
Address Buffers
Address
Register
Burst
Counter
A11
BA1
BA0
Mode Register
CAS Latency
Data Out Control
Pipe Line
Control
Rev. 0.2 / June. 2005
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