iC-NQC
preliminar y
Rev B1, Page 2/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
DESCRIPTION
iC-NQC is a monolithic A/D converter which, by ap-
plying a count-safe vector follower principle, converts
sine/cosine sensor signals with a selectable resolu-
tion and hysteresis into angle position data.
This absolute value is output via a bidirectional,
synchronous-serial I/O interface in BiSS C protocol
and trails a master clock rate of up to 10 Mbit/s. Alter-
natively, this value can be output so that it is compat-
ible with SSI in Gray or binary code, with or without
error bits. The device also supports double transmis-
sion in SSI ring mode.
Signal periods are logged quickly by a 24-bit period
counter that can supplement the output data with an
upstream multiturn position value.
At the same time any changes in angle are con-
verted into incremental A QUAD B signals. Here, the
minimum transition distance can be stipulated and
adapted to suit the system on hand (cable length, ex-
ternal counter). A synchronized zero index Z is gen-
erated if enabled by PZERO and NZERO.
The front-end amplifiers are configured as instrumen-
tation amplifiers, permitting sensor bridges to be di-
rectly connected without the need for external resis-
tors. Various programmable D/A converters are avail-
able for the conditioning of sine/cosine sensor signals
with regard to offset, amplitude ratio and phase er-
rors (offset compensation by 8-bit DAC, gain ratio by
5-bit DAC, phase compensation by 6-bit DAC).
The front-end gain can be set in stages graded to
suit all common complementary sensor signals from
approximately 20 mVpp to 1.5 Vpp and also non-
complementary sensor signals from 40 mVpp to 3
Vpp respectively.
The device can be configured using two bidirectional
interfaces, the EEPROM interface from a serial EEP-
ROM with I
2
C interface, or the I/O interface in BiSS
C protocol. Free storage space on the EEPROM can
be accessed via BiSS for the storage of additional
data.
After a low voltage reset, iC-NQC reads in the config-
uration data including the check sum (CRC) from the
EEPROM and repeats the process if a CRC error is
detected.
ICHAUS [ IC-HAUS GMBH ]
