X24165
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24165 continues to
output data for each acknowledge received. The read
operation is terminated by the master; by not responding
with an acknowledge and then issuing a
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 2047), the counter “rolls over” to 0 and the
X24165 continues to output data for each acknowledge
received. Refer to Figure 9 for the address,
acknowledge and data transfer sequence.
stop condition.
Figure 9. Sequential Read
SLAVE
ADDRESS
S
T
O
P
BUS ACTIVITY:
MASTER
A
C
K
A
C
K
A
C
K
SDA LINE
BUS ACTIVITY:
X24165
A
C
K
P
DATA n
DATA n+1
DATA n+2
DATA n+x
6551 ILL F13
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
TRANSMITTER/
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
RECEIVER
RECEIVER
6551 ILL F14
8
ICMIC [ IC MICROSYSTEMS ]
