欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24165SMG-2.7 参数 Datasheet PDF下载

X24165SMG-2.7图片预览
型号: X24165SMG-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的2线串行E2PROM带座LockTM保护 [Advanced 2-Wire Serial E2PROM with Block LockTM Protection]
分类和应用: 可编程只读存储器
文件页数/大小: 17 页 / 291 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号X24165SMG-2.7的Datasheet PDF文件第1页浏览型号X24165SMG-2.7的Datasheet PDF文件第2页浏览型号X24165SMG-2.7的Datasheet PDF文件第3页浏览型号X24165SMG-2.7的Datasheet PDF文件第4页浏览型号X24165SMG-2.7的Datasheet PDF文件第6页浏览型号X24165SMG-2.7的Datasheet PDF文件第7页浏览型号X24165SMG-2.7的Datasheet PDF文件第8页浏览型号X24165SMG-2.7的Datasheet PDF文件第9页  
X24165
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next three bits are the device select bits. A system could
have up to eight X24165’s on the bus. The eight
addresses are defined by the state of the S
0
, S
1
and S
2
inputs. S
1
of the slave address must be the inverse
The last bit of the slave address defines the operation to be
performed. When set HIGH a read operation is
selected, when set LOW a write operation is selected.
Following the start condition, the X24165 monitors the SDA
bus comparing the slave address being transmitted
of the S
1
input pin.
Figure 4. Slave Address
DEVICE
TYPE
with its slave address device type identifier. Upon a
correct compare the X24165 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24165 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
IDENTIFIER
DEVICE
SELECT
HIGH ORDER
WORD
ADDRESS
1
S
2
S
1
S
0
A10
A9
A8
R/W
For a write operation, the X24165 requires a second ad-
dress field. This address field is the word address, com-
prised of eight bits, providing access to any one of 2048
words in the array. Upon receipt of the word address, the
X24165 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowledge
6551 ILL F07.2
The next three bits of the slave address are an extension
of the array’s address and are concatenated with
the eight bits of address in the word address field,
providing direct access to the whole 2048 x 8 array.
The master then terminates the transfer by generating a
stop condition, at which time the X24165 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24165 inputs
are disabled, and the device will not respond to any requests
from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
Figure 5. Byte Write
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
SDA LINE
BUS ACTIVITY:
X24165
S
A
C
K
A
C
K
A
C
K
P
6551 ILL F08
5