X24C01
WRITE OPERATIONS
the page address. The X24C01 is capable of a four byte page
write operation. It is initiated in the same manner as
the byte write operation, but instead of terminating the
transfer of data after the first data byte, the master can
Byte Write
To initiate a write operation, the master sends a start
condition followed by a seven bit word address and a write
bit. The X24C01 responds with an acknowledge, then waits
for eight bits of data and then responds with an
transmit up to three more bytes. After the receipt of each data
byte, the X24C01 will respond with an acknowledge.
After the receipt of each data byte, the two low order address
bits are internally incremented by one. The high
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24C01
order five bits of the address remain constant. If the
master should transmit more than four data bytes prior
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress, the X24C01
to generating the stop condition, the address counter will “roll
over” and the previously transmitted data will be
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 4 for the
address, acknowledge and data transfer sequence.
overwritten. As with the byte write operation, all inputs are
disabled until completion of the internal write cycle.
Refer to Figure 5 for the address, acknowledge and data
transfer sequence.
Page Write
The most significant five bits of the word address define
Figure 4. Byte Write
S
T
A
R
T
S
T
WORD
ADDRESS (n)
BUS ACTIVITY:
SDA LINE
DATA n
O
P
S
P
A
C
K
A
C
K
L
S
B
M
S
B
R
/
BUS ACTIVITY:
X24C01
W
3837 FHD F09
Figure 5. Page Write
S
T
A
R
T
S
T
WORD
ADDRESS (n)
BUS ACTIVITY:
DATA n
DATA n+1
DATA n+3
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
L
S
B
M
S
B
R
/
BUS ACTIVITY:
X24C01
W
3837 FHD F10
5
ICMIC [ IC MICROSYSTEMS ]
