Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
15
8
Units
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
Refer to NOTE 1
I
OH
= -16mA
I
OH
= -100uA
Refer to NOTE 1
V
OL
Output Low Voltage
I
OL
= 16mA
I
OL
= 100uA
-5
2.6
2.9
3
0.5
0.25
0.15
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
15
8
Units
V
V
mA
mA
8304AM
www.icst.com/products/hiperclocks.html
3
REV. F SEPTEMBER 13, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
