Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
REVISION HISTORY SHEET
Description of Change
• Revised tp
LH
(Propagation Delay) row from 2.3 Min. to 2 Min.
• Deleted tp
HL
row.
• Revised tsk(o) (Output Skew) row from 35 Max. to 80 Max.
• Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max.
• General note changed from "...measured at 166MHz..." to
" ...measured at 150MHz..."
• Revised tp
LH
(Propagation Delay) row from 2.6 Min. to 2.3 Min.
• Deleted tp
HL
row.
• Revised tsk(o) (Output Skew) row from 35 Max. to 85 Max.
• Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max.
• General note changed from "...measured at 166MHz..." to
" ...measured at 150MHz..."
• In AC table, revised tsk(o) row from 80ps Max. to 45ps Max.
Added f = 133MHz in Test Conditions column.
• In odc row, deleted test conditions.
• In notes, changed 150MHz to f
MAX.
• In AC table, revised tsk(o) row from 80ps Max. to 60ps Max.
Added f = 133MHz in Test Conditions column.
• In odc row, deleted test conditions
• In notes, changed 150MHz to f
MAX.
In the Ordering Information table, Marking column, revised marking to read
8304AM from ICS8304AM.
LVCMOS/LVTTL DC Characteristics Table, added I
OH
and I
OL
Test Conditions
to V
OH
and V
OL
rows.
• Pin Assignment - adjusted dimensions.
• Pin Descriptions - changed V
DD
description to Core supply pin.
• Pin Characteristics - changed C
IN
max 4pF to typical 4pF.
Deleted R
PULLUP
row.
Added 5
Ω
min. and 12
Ω
max. to R
OUT
.
• Power Supply tables - changed V
DD
parameter from Power to Core.
• Ordering Information table - added "Lead Free/Annealed" marking.
Updated format throughout the data sheet.
Featues section, changed Maximum output frequency bullet from 166MHz to
200MHz.
3.3V AC Table - changed 166MHz max. to 200MHz max.
Added another line for Propagation Delay.
Changed test conditions in Output Duty Cycle from 166MHz to 189.5MHz.
3.3V AC Table - changed 166MHz max. to 189.5MHz max.
Added another line for Propagation Delay.
Changed test conditions in Output Duty Cycle from 166MHz to 189.5MH
• Ordering Information table - added "Lead Free" marking.
Date
12/4/01
Rev
B
Table
T4A
Page
3
T4B
4
C
T4A
3
12/11/01
T4B
4
C
D
T7
T3B
10
3
1
2
2
3/11/02
4/4/02
T1
T2
E
T3A & T3C
T7
4/13/04
3&4
8
1
T4A
F
T4B
4
6/1/04
4
F
T7
8
9/13/04
8304AM
www.icst.com/products/hiperclocks.html
9
REV. F SEPTEMBER 13, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
