Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
2.1
0.5
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
T
ABLE
3D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
166MHz < f
≤
189.5MHz
ƒ = 133MHz
2.0
2.0
Test Conditions
Minimum
Typical
Maximum
200
3.3
3.4
45
500
500
500
60
Units
MHz
ns
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
189.5MHz
40
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
166MHz < f
≤
189.5MHz
ƒ = 133MHz
2.3
2.15
Test Conditions
Minimum
Typical
Maximum
189.5
3.7
3.55
60
500
500
500
60
Units
MHz
ns
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
189.5MHz
40
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM
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4
REV. F SEPTEMBER 13, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
