Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
8523AGI-03
www.icst.com/products/hiperclocks.html
7
REV. A OCTOBER 5, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
