Integrated
Circuit
Systems, Inc.
ICS8523I-03
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Test Conditions
Minimum
0.7
0
0.4
Typical
Maximum
1.0
0.4
1.0
Units
V
V
V
T
ABLE
4D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ƒ > 200MHz
150
45
50
IJ 650MHz
0.9
1.2
Test Conditions
Minimum
Typical
Maximum
650
1.5
50
400
500
55
52
Units
MHz
ns
ps
ps
ps
%
%
t
sk(o)
t
sk(pp)
t
R
/ t
F
o dc
IJ 200MHz
48
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8523AGI-03
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 5, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
