Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
A
PPLICATION
I
NFORMATION
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required.
Figure 1
illus-
trates how a 24Ω resistor along with a 10µF and a .01µF by-
pass capacitor should be connected to each V
DDA
pin.
3.3V
V
DD
.01µF
V
DDA
.01µF
10µF
24Ω
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
9DB202CG
www.icst.com/products/hiperclocks.html
7
REV. A OCTOBER 6, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
