Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
Test Conditions
Minimum
12
680
65
-10
250
10
550
Typical
14
Maximum
16
Units
mA
V
V
µA
mV
T
ABLE
4D. HCSL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C, RREF = 475Ω
Symbol
I
OH
V
OH
V
OL
I
OZ
V
OX
Parameter
Output Current
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Crossover Voltage
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C, RREF = 475Ω
Symbol
f
MAX
Parameter
Output Frequency
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
RMS Phase Jitter
(Random); NOTE 3
Output Rise/Fall Time
Outputs @ Different Frequencies
Outputs @ Same Frequencies
Integration Range: 1.5MHz - 22MHz
20% to 80%
300
2.42
1100
52
50
Test Conditions
Minimum
Typical
Maximum
140
110
110
50
Units
MHz
ps
ps
ps
ps
ps
%
t
sk(o)
t
jit(cc)
t
jit(Ø)
t
R
/ t
F
o dc
Output Duty Cycle
48
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
9DB202CG
www.icst.com/products/hiperclocks.html
4
REV. A OCTOBER 6, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
