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ICS9DB202CGLF 参数 Datasheet PDF下载

ICS9DB202CGLF图片预览
型号: ICS9DB202CGLF
PDF下载: 下载PDF文件 查看货源
内容描述: 两个0.7V电流模式差分HCSL输出对, 1差分时钟输入 [Two 0.7V current mode differential HCSL output pairs, 1 differential clock input]
分类和应用: 逻辑集成电路光电二极管驱动时钟
文件页数/大小: 11 页 / 263 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS9DB202  
Integrated  
Circuit  
Systems, Inc.  
PCI EXPRESS  
JITTER  
ATTENUATOR  
DIFFERENTIAL CLOCK INPUT INTERFACE  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the  
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.  
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS  
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver  
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.  
3.3V  
3.3V  
3.3V  
1.8V  
Zo = 50 Ohm  
CLK  
Zo = 50 Ohm  
CLK  
Zo = 50 Ohm  
nCLK  
Zo = 50 Ohm  
HiPerClockS  
Input  
LVPECL  
nCLK  
HiPerClockS  
Input  
LVHSTL  
R1  
50  
R2  
50  
ICS  
HiPerClockS  
R1  
50  
R2  
50  
LVHSTL Driver  
R3  
50  
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY  
ICS HIPERCLOCKS LVHSTL DRIVER  
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50 Ohm  
3.3V  
R3  
125  
R4  
125  
LVDS_Driver  
Zo = 50 Ohm  
Zo = 50 Ohm  
CLK  
CLK  
R1  
100  
nCLK  
Receiv er  
nCLK  
HiPerClockS  
Input  
Zo = 50 Ohm  
LVPECL  
R1  
84  
R2  
84  
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY  
3.3V LVPECL DRIVER  
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY  
3.3V LVDS DRIVER  
9DB202CG  
www.icst.com/products/hiperclocks.html  
REV. A OCTOBER 6, 2004  
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