IC41C16100S
IC41LV16100S
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
I
IL
I
IO
V
OH
V
OL
I
CC
1
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Test Condition
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
= –5.0 mA (5V)
I
OH
= –2.0 mA (3.3V)
I
OL
= 4.2 mA (5V)
I
OL
= 2.0 mA (3.3V)
RAS, LCAS, UCAS
≥
V
IH
Commerical
Extended
I
CC
2
I
CC
3
Standby Current: CMOS
RAS, LCAS, UCAS
≥
V
CC
– 0.2V
5V
3.3V
5V
3.3V
5V
3.3V
-45
-50
-60
-45
-50
-60
-45
-50
-60
-45
-50
-60
—
Speed
Min.
–5
–5
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
5
5
—
0.4
2
1
3
2
1
0.5
190
160
145
100
90
80
180
160
145
180
160
145
300
Unit
µA
µA
V
V
mA
mA
mA
mA
Operating Current:
RAS, LCAS, UCAS,
(2,3,4)
Random Read/Write
Address Cycling, t
RC
= t
RC
(min.)
Average Power Supply Current
Operating Current:
RAS
= V
IL
,
LCAS, UCAS,
(2,3,4)
EDO Page Mode
Cycling t
PC
= t
PC
(min.)
Average Power Supply Current
Refresh Current:
RAS
Cycling,
LCAS, UCAS
≥
V
IH
(2,3)
RAS-Only
t
RC
= t
RC
(min.)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
Self Refresh Current
RAS, LCAS, UCAS
Cycling
t
RC
= t
RC
(min.)
Self Refresh mode
I
CC
4
mA
I
CC
5
mA
I
CC
6
mA
I
CCS
µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR010-0D 11/26/2004
7
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
