IC41C16105S
IC41LV16105S
TRUTH TABLE
ꢀunction
RAS
LCAS UCAS
WE
X
OE
X
Address tR/tC I/O
Standby
H
L
L
H
L
L
H
L
X
High-Z
Read: Word
Read: Lower Byte
H
L
ROW/COL
ROW/COL
DOUT
H
H
L
Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L
L
L
L
L
L
L
X
X
ROW/COL
ROW/COL
DIN
Write: Lower Byte (Early Write)
H
Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
Read-Write(1,2)
L
L
H
L
L
L
L
X
ROW/COL
ROW/COL
Lower Byte, High-Z
Upper Byte, DIN
H
®
L
L
®
H
DOUT, DIN
Hidden Refresh
Read(2)
Write(1,3)
L
®H®
L
L
L
L
L
L
H
L
L
ROW/COL
ROW/COL
DOUT
DOUT
L®H®
X
RAS-Only Refresh
CBR Refresh(4)
L
H
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
H
®
L
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
3
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
