IC41C16105S
IC41LV16105S
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V ꢀ VIN ꢀ Vcc
Other inputs not under test = 0V
5
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V ꢀ VOUT ꢀ Vcc
5
2.4
5
µA
V
VOH
VOL
ICC1
IOH = 5.0 mA (5V)
IOH = 2.0 mA (3.3V)
0.4
IOL = 4.2 mA (5V)
IOL = 2.0 mA (3.3V)
V
RAS, LCAS, UCAS > VIH
Commerical
5V
2mA
3.3V
Extended & Idustrial 5V
3.3V
1
3
2
mA
ICC2
ICC3
Standby Current: CMOS
RAS, LCAS, UCAS > VCC 0.2V
5V
3.3V
1
0.5
mA
mA
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
160
145
ICC4
ICC5
ICC6
Operating Current:
<ast Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
90
80
mA
mA
mA
µA
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, LCAS, UCAS > VIH
tRC = tRC (min.)
-50
-60
160
145
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
160
145
ICCS
Self Refresh Current
Self Refresh mode
5V
3.3V
650
300
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREꢀ refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each ꢀast page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR011-0A 05/23/2001
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
